Tri-state Phase/Frequency Comparator block
This block realizes the phase/frequency comparison between of its two event inputs.
D flip-flop tri-State Phase/Frequency Comparator
At each event the state of the regular outputs
can change according to the last state.
When the input events are synchronized, the high state is realized after one delay.
That block realizes the following algorithm that is a derived model
from the model find in .
More descriptions of this Phase/Frequency comparator can be found in
the reference .
- Lenght of anti-backlash pulse (0:No pulse/Length of pulse [s])
The duration of the anti-backlash pulse. If set 0 then the output event port and the third input event port of that block are disable.
Type 'vec' of size 1.
- always active: no
- direct-feedthrough: no
- zero-crossing: no
- mode: no
- regular outputs:
- port 1 : size [1,1] / type 1
- port 2 : size [1,1] / type 1
- number/sizes of activation inputs: 2
- number/sizes of activation outputs: 0
- continuous-time state: no
- discrete-time state: yes
- object discrete-time state: no
- name of computational function: cpf
- MODNUMCOS/macros/scicos_blocks/Pll/CPF_f.sci [view code]
A. Demir, ``Analysis and simulation of noise in nonlinear electronic circuits
and system,'' Ph.D. dissertation, University of California, Berkeley, 1997.
M. Curtin and P. Brien, ``Phase-locked loops for high-frequency receivers and
transmitters,'' Analog Dialogue, vol. 33, 1999. [Online]. Available: