Scicos Block
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Memory discrete shift register for vectorial signal block





This block is a right shift register. It delays ouput data from input data by a given number of samples. Internal discrete states store the delayed samples and for this inital delayed samples, the values of output element are zero.
The following figure illustrates the case where the input port has a size of 5 samples and where the number of right shift is 2.

Figure 1: Right Shift Register block for in size = 5 and shift = 2.

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A. Layec