Delta-Sigma modulator block
This block can realize a first, second or third order
modulator[1] with the following internal structure :
Figure 1: Diagram of a third order

modulator
- Size of inputs
If set greater than 1, then perform modulation of an input vector of discrete variables. (sample-based model)
Properties : Type 'vec' of size 1.
- Amplitude of input modulator
Maximal amplitude of the input(s) of modulator.
Properties : Type 'vec' of size 1.
- Order of modulator(1,2 or 3)
Define the order of the modulator. Must be 1,2 or 3.
Properties : Type 'vec' of size 1.
- Type of output(0:Regular/-1;1:Scaled)
Align (center if choice is set to 0) or not the binary output data stream.
Properties : Type 'vec' of size 1.
- Enable Quantization error output?(0:No/1:Yes)
Allow a second regular output that gives the output quantization error of the modulator.
Properties : Type 'vec' of size 1.
- Inherit (no:0, yes:1)
Herits events by its regular input ports (disable the event input port).
Properties : Type 'vec' of size 1.
- always active: no
- direct-feedthrough: yes
- zero-crossing: no
- mode: no
- regular inputs:
- port 1 : size [1,1] / type 1
- regular outputs:
- port 1 : size [1,1] / type 1
- number/sizes of activation inputs: 1
- number/sizes of activation outputs: 0
- continuous-time state: no
- discrete-time state: yes
- object discrete-time state: no
- name of computational function: sdblk
- MODNUMCOS/macros/scicos_blocks/Pll/SDBLK_c.sci [view code]
A. Layec
- [1]
S. Park, ``Principles of sigma-delta modulation for analog-to-digital
converters,''
Applications report, Motorola.